1. Field of the Invention
The present invention relates to a data read circuit of a semiconductor device.
2. Description of the Related Art
The development of microtechnology of semiconductor elements in recent years has been accompanied by the increasing scale of the LSI that is composed of these semiconductor elements. This development has been particularly dramatic in the field of semiconductor memory devices. As examples, dynamic random access memory (DRAM) has been put into practical use as semiconductor memory devices having a capacity of 256 megabytes on one chip, as has static random access memory (SRAM) having a capacity of 18 megabytes on one chip.
Referring now to FIG. 1, which shows the construction of a multiport memory cell that employs a single-end mode, it can be seen that in these types of semiconductor memory devices, a reduction in the area of the memory cell is obtained through the use of the single-end mode in the bit lines for read. The single-end mode is a mode for transferring cell data by a single bit line.
FIG. .2 shows an example of the construction of multiport RAM. As shown in FIG. 2, the basic structure of the memory is constituted by providing multiport RAM with: memory cells that are arranged at the intersections of intersecting horizontal lines and vertical lines; word lines 420 ,421˜42n, 430, 431˜43n and 440, 441˜44n for individually selecting row addresses for each port; bit lines 45, 46, 47, and 48 for propagating data of the memory cells; precharging circuit 49 for precharging bit lines 45, 46, 47, and 48; write port column selector 50 for selecting column addresses; read port column selector 51; read circuit 53 at the read port for data that have been propagated on bit lines; data output circuit 55; write circuit 52 at the write port for propagating write data on bit lines; and data input circuit 54.
FIG. 3 shows a timing chart for reading data of the multiport RAM of FIG. 2. Referring now to FIG. 3, as shown in interval A, read bit line 48 that has been precharged by means of precharging circuit 49 is discharged by the data of the memory cell that is selected at timing t1 of the rise of word line 440. In some cases, this potential is determined to be low-level at timing t2 at which this potential falls below the theoretical threshold value of read circuit 53, read signal becoming high level at t3 and data output 18 becoming high level at timing t4. In other cases, the potential of bit line 48 is maintained without change and determined to be high level and data are supplied as output as shown in interval B.
FIG. 4 shows a timing chart for a case in which increase in capacitance of the bit line causes the discharge time to increase. Referring to FIG. 4, an increase in the number of rows of memory causes an increase in the capacitance of the bit line, and it can be seen that the time required for the discharge of bit line 48 (t2˜1) thus increases and the reading speed accordingly decreases.
In order to cope with large capacity, a configuration was adopted in the prior art for enabling high-speed reading in a memory having high capacity in which the memory was divided into a plurality of banks, addresses were selected in bank units, and the data that were read were transferred to the output circuit through a data bus.
Referring to FIG. 5, this configuration comprises: a plurality of memory banks 2 in which memory cells are arranged at each of the intersections of intersecting horizontal lines and vertical lines; row decoder 3 that is connected to each of the memory banks for selecting row addresses; column selector 58 for selecting column addresses; sense amplifier precharging circuit 59 for amplifying data that have been selected by column selector 58 and precharging bit lines; output circuit 60 for supplying the data as output; and data buses 56a and 56b for transferring data between output circuit 60 and sense amplifier precharging circuit 59.
A read operation of this scheme is next described with reference to the timing chart of FIG. 6. Word line 81 of a memory bank that has been selected with bit lines in a precharged state rises at timing t6, bit line 10a is discharged, and at timing t7, the output of the sense amplifier amplifies the data of word line 81. The amplified data are transferred as far as output circuit 60 by means of data buses 56a and 56b and then supplied as output at timing t8, whereby high-speed read is realized in the large-capacity memory. In other words, the division of the memory cell area of the large-capacity memory into a plurality of blocks is a requisite technique for accelerating the reading process.
Another example of accelerating the bit line speed is disclosed in Japanese Patent No. 2892697. The semiconductor memory device disclosed in this publication realizes an increase in speed through the use of a differential sense amplifier, which is typically used in differential-mode bit lines, for amplifying the difference in potential between a reference signal and single-end mode bit lines.
As shown in FIG. 7, which shows the structure of single-port RAM cells, the differential mode refers to a mode in which cell data are propagated on two lines of positive and negative logic, as with the bit lines of single-port RAM.
Japanese Patent Laid-Open No. H10-134578 discloses the insertion on of a buffer circuit in the bit lines between the plurality of blocks into which a memory element unit has been divided for either amplifying and supplying the output or cutting off the output in accordance with the selection of elements of input-side blocks or output-side blocks.
As described in the foregoing explanation regarding a semiconductor memory device of the prior art, a method in which the memory is divided into a plurality of blocks necessitates column selectors for each memory bank unit, and further, a multiport memory necessitates a number of column selectors equal to the number of ports, and the area of the device therefore increases proportionally. Furthermore, column decoders for operating the column selectors are similarly required, and this requirement results in further increase in the chip area.
In addition, regions for the data bus lines for transferring data of each block are also required for each port, further increasing the chip area. In a memory that is frequently used in a multibit construction, such as in a multiport memory, the influence of the area of the data bus regions that are held in bit units is particularly significant.
In the example of Japanese Patent No. 2892697, which uses reference signals, and further, uses differential sense amplifiers, the amount of discharge of bit lines required to obtain the desired differential potential is approximately twice that of the differential scheme, and increasing speed when the capacitance is high is therefore problematic.
In the construction disclosed in Japanese Patent Laid-Open No. H10-134578, moreover, an increase in the amount of capacitance that accumulates in bit lines slows the change in the output signal of the buffer circuit inserted between bit lines, hindering an increase in speed.